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advance information ?2001 silicon storage technology, inc. s71170-03-000 12/01 368 1 sst, the sst logo, and superflash are trademarks registered by silicon storage technology, inc. in the u.s. patent and trademar k office. in-application programming, iap, and softpartition are trademarks of silicon storage technology, inc. these specifications are subject to change without notice. features: ? 8-bit mcu core ? enhanced 6502 microprocessor megacell emulating the reduced 6805 instruction set 4 mhz typical oscillator clock frequency 8 mhz maximum oscillator clock frequency low voltage operation: 2.2-3.2v 20 re-configurable general purpose i/o leads superflash memory ? 16 kbyte of flash memory ? 128 byte sectors for softpartition ? 100,000 endurance cycles (typical) ? 100 years data retention ? fast write: - chip-erase: 70 ms (typical) - sector-erase: 18 ms (typical) - byte-program: 60 s (typical) ? in-application programming (iap) external host programming mode for programmer support ? jedec standard command sets 352 byte on-chip sram in-system programming (isp) support through firmware ir input pin for learning mode carrier modulator transmitter ? supports baseband, pulse length modulator (plm), and frequency shift keying (fsk) core timer / counter ? 14-stage multifunctional ripple counter ? includes timer overflow, por, rti, and cwt external reset input and low power pins power management ? hardware enable bits programmable by software for entering stop and idle modes package available ? 28-lead soic product description the sst65p542r is a member of sst?s 8-bit application specific microcontroller family targeted for ir remote con- troller applications. the sst65p542r microcontroller provides high functional- ity to infrared remote controller products. the device offers flexibility to store different remote control configurations for controlling multiple appliances. the configurations are either programmed at the factory during the manufacturing process or downloaded through firmware. using sst?s superflash nonvolatile memory technology, the sst65p542r enhances the functionality and reduces the cost of conventional universal remote controller devices by integrating multiple functions of a remote controller sys- tem in a single chip solution. the built-in led i/o ports can directly drive led indicators. the ir transmitter port drives signals to the infrared transmitter, which, in turn, remotely controls the appliances. the softpartition architecture allows seamless flash mem- ory partitioning of the program code, protocol tables, and user data in the small granularity of 128 byte sectors. the small sector size and fast write capability of the device greatly decreases the time and power when altering the contents of the flash memory. the highly reliable, patented superflash technology provides significant advantage over conventional flash memory technology. these advantages translate into significant cost saving and reliability benefits for the customers. remote controller mcu sst65p542r sst65p542rmicrocontroller
2 advance information remote controller mcu sst65p542r ?2001 silicon storage technology, inc. s71170-03-000 12/01 368 table of contents product description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 list of figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 list of tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.0 functional blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.0 pin assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.1 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.0 i/o registers and memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.1 i/o registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.2 sram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.3 superflash memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.0 parallel input/output ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.1 port a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.2 port b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.3 port c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.0 flash memory programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.1 in-application programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.1.1 chip-erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.1.2 sector-erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.1.3 byte-program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.2 external host programming mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.2.1 external host mode read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.2.2 external host mode write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.2.3 external host mode byte-program operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.2.4 external host mode chip-erase operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.2.5 external host mode sector-erase operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2 5.2.6 operation status detection - program timer method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.2.7 operation status detection - ry/by# method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.2.8 exiting the external host programming mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.2.9 flash read protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.0 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.1 external reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.2 external low power reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.3 internal power-on and brown-out reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.4 cop watchdog timer reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.5 illegal address reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
advance information remote controller mcu sst65p542r 3 ?2001 silicon storage technology, inc. s71170-03-000 12/01 368 7.0 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.1 software interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.2 external interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.3 cmt interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.4 core timer interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 8.0 operation modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8.1 user mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8.2 learning mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 9.0 peripherals and others . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 9.1 core timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 9.2 carrier modulator transmitter (cmt). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 9.3 clock input options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 9.4 crystal/ceramic resonator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 9.5 external clock drive. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 10.0 power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 10.1 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 10.2 idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 11.0 electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 11.1 absolute maximum stress ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 11.2 reliability characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 11.3 dc specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 11.4 dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 11.5 ac electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 12.0 product ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 12.1 valid combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 13.0 packaging diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
4 advance information remote controller mcu sst65p542r ?2001 silicon storage technology, inc. s71170-03-000 12/01 368 list of figures figure 2-1: pin assignments for 28-lead soic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 3-1: memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 4-1: port b interrupt and pull-up options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 6-1: reset block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 9-1: using the crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 9-2: external clock drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 10-1: stop mode and idle mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 11-1: external host programming mode - setup cycle timing diagram. . . . . . . . . . . . . . . . . . . . 32 figure 11-2: external host programming mode - read cycle timing diagram . . . . . . . . . . . . . . . . . . . . 32 figure 11-3: external host programming mode - write cycle timing diagram . . . . . . . . . . . . . . . . . . . . 33 figure 11-4: external host programming mode - chip-erase timing diagram . . . . . . . . . . . . . . . . . . . . 33 figure 11-5: external host programming mode sector-erase timing diagram . . . . . . . . . . . . . . . . . . . . 34 figure 11-6: external host programming mode byte-program timing diagram . . . . . . . . . . . . . . . . . . . 34 figure 11-7: ac input/output reference waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 11-8: a test load example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 11-9: byte-program command sequence for external host programming mode . . . . . . . . . . . . 36 figure 11-10: wait options for external host programming mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 11-11: chip-/sector-erase command sequence for external host programming mode . . . . . . . 38 list of tables table 2-1: pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 3-1: register descriptions and bit definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 3-5: interrupt/reset sector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 5-1: sffr commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 5-2: external host programming mode pin descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 5-3: external host programming mode pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 5-4: software command sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 8-1: pin assignment for different operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 11-1: reliability characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 11-2: recommended dc operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 11-3: dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 11-4: control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 11-5: external host programming-mode timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
advance information remote controller mcu sst65p542r 5 ?2001 silicon storage technology, inc. s71170-03-000 12/01 368 1.0 functional blocks irq# superflash memory 16k x8 interrupt control mcu core ram 352k x8 port a port b timer/counter interrupt iro carrier modulator transmitter real-time counter core timer / counter 368 ill b1.8 cop watchdog timer port c f unctional b lock d iagram
6 advance information remote controller mcu sst65p542r ?2001 silicon storage technology, inc. s71170-03-000 12/01 368 2.0 pin assignments figure 2-1: p in a ssignments for 28- lead soic 2.1 pin descriptions pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 pa 0 pa 1 pa 2 pa 3 pa 4 pa 5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 osc1 osc2 v dd irq# rst# iro v ss lprst# pc3 pc2 pc1 pc0 pa 7 pa 6 28-lead soic top view 368 28-soic ill p01.5 table 2-1: p in d escriptions symbol type name and functions pa[7:0] i/o 1 1. i = input, o = output port a: the state of any pin in port a is software programmable and every line is configured as an input during any reset. pb[7:0] i/o port b: the state of any pin in port b is software programmable and every line is configured as an input during any reset. each i/o line contains a programmable interrupt/pull-up for keyscan. pc[3:0] i/o port c: every pin in port c is a high-current pin and its state is software programmable. all lines are configured as inputs during any reset. iro o iro: suitable for driving ir led biasing logic, the iro pin is the high-current source and sink out- put of the carrier modulator transmitter subsystem. default state is low after any reset. lprst# i low-power reset: an active-low pin, lprst# function sets mcu to low-power reset mode. once the device is in low-power reset mode, it is held in reset with all processor clocks and crystal oscillator halted. an internal schmitt trigger is included in the lprst# pin to improve noise immunity. rst# i reset: by setting the rst# pin low, the device is reset to a default state. an internal schmitt trig- ger is included in the rst# pin to improve noise immunity. osc1 i oscillator 1,2: these 2 pins interface with external oscillator circuits. a crystal osc2 o resonator, a ceramic resonator, or an external clock signal can be used. irq# i interrupt request: the irq# is negative edge-sensitive triggered. an internal schmitt trigger is included in the irq# pin to improve noise immunity. v dd pwr power supply: supply voltage (2.2-3.2v) v ss pwr ground: circuit ground. (0v reference) t2-1.14 368
advance information remote controller mcu sst65p542r 7 ?2001 silicon storage technology, inc. s71170-03-000 12/01 368 3.0 i/o registers and memory organization the sst65p542r has a total of 64 kbyte of addressable memory space. a memory map is located in figure 3-1. the on-chip memory consists of 32 bytes of i/o registers, 352 bytes of sram, 16 kbyte of user flash memory and 128 bytes of user vectors. figure 3-1: m emory m ap ff7fh ff80h bfffh c000h flash memory (128 sectors) 127 sectors (128 bytes per sector) user memory 0000h 001fh 0020h 017fh 0180h ffffh 368 ill f02.9 i/o registers 352 bytes sram user vector 16,256 bytes 0180h bfffh reserved reserved reserved 3fefh ff80h fff6h ffffh cwt reset flash memory read protection reset and interrupt vectors ff81h fff5h core timer vector - (high byte) core timer vector - (low byte) cmt vector (high byte) cmt vector (low byte) irq/port b vector (high byte) irq/port b vector (low byte) swi vector (high byte) swi vector (low byte) reset vector (high byte) reset vector (low byte) fff6h fff7h fff8h fff9h fffah fffbh fffch fffdh fffeh ffffh 3ff0h 3ff1h
8 advance information remote controller mcu sst65p542r ?2001 silicon storage technology, inc. s71170-03-000 12/01 368 3.1 i/o registers the 32 bytes of i/o registers occupy address locations from 0000h to 001fh that include general purpose i/o reg- isters, the superflash function register, and on-chip peripheral control registers. table 3-1: r egister d escriptions and b it d efinitions (1 of 2) symbol 1 description direct address bit address, bit symbol reset value 2,3 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 porta port a data register 0000h pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 00h portb port b data register 0001h pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 00h portc port c data register 0002h - - - - pc3 pc2 pc1 pc0 00h - reserved 0003h - - - - - - - - - ddra port a data direction register 0004h ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 00h ddrb port b data direction register 0005h ddrb7 ddrb6 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 00h ddrc port c data direction register 0006h - - - - ddrc3 ddrc2 ddrc1 ddrc0 00h - reserved 0007h - - - - - - - - - ctscr core timer control and status register 0008h ctof rtif tofe rtie tofc rtfc rt1 rt0 03h ctcr core timer counter register 0009h ctd7 ctd6 ctd5 ctd4 ctd3 ctd2 ctd1 ctd0 00h pbic port b interrupt control register 000ah inprb7 inprb6 inprb5 inprb4 i nprb3 inprb2 inprb1 inprb0 00h sffr superflash function register 000bh pren meren seren - prog mera sera - 00h pbpuc port b pull-up control register 000ch - - - - - - pu1 pu0 03h cwtc cwt control register 000dh - - - - - - - cwt_en 00000001b - reserved 000eh - - - - - - - - - - reserved 000fh - - - - - - - - - chr1 carrier generator high data register 1 0010h iroln cmtpol ph5 ph4 ph3 ph2 ph1 ph0 00uuuuuub clr1 carrier generator low data register 1 0011h irolp - pl5 pl4 pl3 pl2 pl1 pl0 00uuuuuub chr2 carrier generator high data register 2 0012h - - sh5 sh4 sh3 sh2 sh1 sh0 00uuuuuub
advance information remote controller mcu sst65p542r 9 ?2001 silicon storage technology, inc. s71170-03-000 12/01 368 clr2 carrier generator low data register 2 0013h - - sl5 sl4 sl3 sl2 sl1 sl0 00uuuuuub mcsr modulator control and status register 0014h eoc div2 eimsk exspc base mode eocie mcgen 00h mdr1 modulator data register 1 0015h mb11 mb10 mb9 mb8 sb11 sb10 sb9 sb8 uuuuuuuub mdr2 modulator data register 2 0016h mb7 mb6 mb5 mb4 mb3 mb2 mb1 mb0 uuuuuuuub mdr3 modulator data register 3 0017h sb7 sb6 sb5 sb4 sb3 sb2 sb1 sb0 uuuuuuuub pscr power saving control register 0018h en - - - - - stop idl 10000011b - reserved 0019h - - - - - - - - - - reserved 001ah - - - - - - - - - - reserved 001bh - - - - - - - - - - reserved 001ch - - - - - - - - - - reserved 001dh - - - - - - - - - - reserved 001eh - - - - - - - - - - reserved 001fh - - - - - - - - - cwtc cop watchdog timer reset register 3ff0h - - - - - - - cwt_clr 01h t3-1.8 368 1. ?-? = reserved bits 2. ?u? = unaffected by any reset 3. these registers can be reset by either external or internal reset. table 3-1: r egister d escriptions and b it d efinitions (c ontinued ) (2 of 2) symbol 1 description direct address bit address, bit symbol reset value 2,3 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
10 advance information remote controller mcu sst65p542r ?2001 silicon storage technology, inc. s71170-03-000 12/01 368 symbol function pa[7:0] port a data register bit 0 to 7. these bits are for both reading and writing. write the data to this register will output data to port a pins when it?s in output mode. if the pins are set to input mode, only the output data register is updated, port a pins are tri-stated. reading the data from this register will read the state of port a pins when set in input mode. if the pins are set to output mode, it reads the output data register. see table 3-2 for details. for a detailed explanation of each parallel i/o port, please refer to section 4.0, ?parallel input/output ports? on page 20. symbol function pb[7:0] port b data register bit 0 to 7. these bits are for both reading and writing. writing data to this register will output data to port b pins when it?s in output mode. if the pins are set to input mode, only the output data register is updated, port b pins are tri-stated. reading the data from this register will read the state of port b pins when set in input mode. if the pins are set to output mode, it reads the output data register. see table 3-2 for details. symbol function pc[3:0] port c data register bit 0 to 3. these bits are for both reading and writing. writing data to this register will output data to port c pins when it?s in output mode. if the pins are set to input mode, only output data register is updated, port c pins are tri-stated. reading data from this register will read the state of port c pins when set in input mode. if the pins are set to output mode, it reads the output data register. see table 3-2 for details. port a data register (porta) location 76543210 reset value 0000h pa 7 pa 6 pa 5 pa 4 pa 3 pa 2 pa 1 pa 0 00h port b data register (portb) location 76543210 reset value 0001h pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 00h port c data register (portc) location 76543210 reset value 0003h - - - - ddrc3 ddrc2 ddrc1 ddrc0 00h table 3-2: i/o p in f unctions as g eneral p urpose i/o access ddra, ddrb, ddrc mode i/o pin functions write 0 input data is written into the output data register. write 1 output data is written into the output data register and output to the i/o pins. read 0 input the state of i/o is read read 1 output the output data register is read t3-2.0 368
advance information remote controller mcu sst65p542r 11 ?2001 silicon storage technology, inc. s71170-03-000 12/01 368 symbol function ddra[7:0] port a data direction register bit 0 to 7. these bits are for both reading and writing. see table 3-2 for details. 0: port a is input 1: port a is output symbol function ddrb[7:0] port b data direction register bit 0 to 7. these bits are for both reading and writing. see table 3-2 for details. 0: port b is input 1: port b is output symbol function ddrc[3:0] port c data direction register bit 0 to 3. these bits are for both reading and writing. see table 3-2 for details. 0: port c is input 1: port c is output symbol function inprb[7:0] port b interrupt control bits 0: interrupt is enabled 1: interrupt is disabled port a data direction register (ddra) location 76543210 reset value 0004h ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 00h port b data direction register (ddrb) location 76543210 reset value 0005h ddrb7 ddrb6 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 00h port c data direction register (ddrc) location 76543210 reset value 0006h ----pc3pc2pc1pc0 00h port b interrupt control register (pbic) location 76543210 reset value 000ah inprb7 inprb6 inprb5 inprb4 inprb3 inprb2 inprb1 inprb0 00h
12 advance information remote controller mcu sst65p542r ?2001 silicon storage technology, inc. s71170-03-000 12/01 368 symbol function pu1,pu0 port b pull-up control bits. the following table shows pull-up strength. defaults to strong pull-up when reset. port b pull-up control register (pbpuc) location 76543210 reset value 000ch ------pu1pu0 03h table 3-3: p ull - up c ontrol b it d escription pu1 pu0 pull-up 0 0 no pull-up for port b bit 0 1 weak pull-up for each port b bit 1 0 weak pull-up for each port b bit 1 1 strong pull-up for each port b bit 1 1. default value after power-on or reset t3-3.1 368
advance information remote controller mcu sst65p542r 13 ?2001 silicon storage technology, inc. s71170-03-000 12/01 368 symbol function ctof core timer overflow bit. ctof is a real-only status bit, this bit is set when the 8-bit ripple counter rolls over from ffh to 00h. writing to this bit has not effect. reset clears ctof. ctof set to zero by writing a one to tofc. rtif real-time interrupt bit. rtif is a read-only status bit. writing has no effect on this bit. reset clears rtif. the real time interrupt circuit consists of a divider and a one-of-four selector. the input clock frequency that drives the rti circuit is e/2 12 with three additional divider stages that allows a maximum interrupt period of 16 ms at the internal peripheral clock rate of 2.048 mhz. 0: writing a one to rtfc clears the rtif. 1: when the output of the chosen (one-of-four selector) stage goes active. tofe timer overflow enable bit. tofe is statuses bit for both read and write. reset clears this bit. 0: if the ctof is not set or no timer overflow occurs. 1: if the ctof is set and a cpu interrupt request is generated rtie real time interrupt enable bit. rtie is a status bit for both read and write. reset clears this bit. 0: if the rtif is not set. 1: if the rtif is set and a cpu interrupt request is generated. tofc timer overflow flag clear bit. this bit is for writing only. 0: writing a zero has no effect on the ctof bit. this bit always reads as zero. 1: when a one is written to this bit, ctof is cleared. rtfc real time interrupt flag clear bit. this bit is for writing only. 0: writing a zero has no effect on the rtif bit. this bit always reads as zero. 1: when a one is written to this bit, rtif is cleared. rt[1:0] real time interrupt rate select bit. these two bits select one of four taps from the interrupt logic. see table 3-4. reset sets these two bits, which selects the lowest periodic rate and gives the maximum. care should be taken when altering rt0 and rt1 if the timeout period is imminent or uncertain. the cwt should be cleared before changing rti taps. if the selected tap is modified during a cycle in which the counter is switching, an rtif could be missed or an additional one could be generated. core timer control status register (ctcsr) location 76543210 reset value 0008h ctof rtif tofe rtie tofc rtfc rt1 rt0 03h table 3-4: rti and cwt r ates at 4.096 mh z o scillator , p rescaler =1 rti rate rt1-rt0 minimum cwt rates maximum cwt rates 2ms 2 12 /e 1 1. e is the internal peripheral clock frequency and e = f osc /2 00 (2 15 -2 12 )/e 14ms (2 15 )/e 16ms 4ms 2 13 /e 01 (2 16 -2 13 )/e 28ms (2 16 )/e 32ms 8ms 2 14 /e 10 (2 17 -2 14 )/e 56ms (2 17 )/e 64ms 16ms 2 15 /e 11 (2 18 -2 15 )/e 112ms (2 18 )/e 128ms t3-4.2 368
14 advance information remote controller mcu sst65p542r ?2001 silicon storage technology, inc. s71170-03-000 12/01 368 symbol function ctd[7:0] the core timer counter register bit 0 to bit 7. this is a read only status register in which contains the current value of the 8-bit ripple counter. this counter is clocked by the cpu clock (e/4) and can be used for various functions, including a software input capture. extended time can be achieved by using the timer overflow function to increment a variable to simulate a 16-bit counter. symbol function pren byte program enable bit. 0: disable the byte program. 1: enable the byte program. meren mass (chip) program enable. 0: disable the mass (chip) erase or program. 1: enable the mass (chip) erase or program. seren sector program enable. 0: disable the sector erase or program. 1: enable the sector erase or program. prog byte program control bit. 0: not performs the byte program 1: performs the byte program. mera mass (chip) program active bit. 0: not performs the chip program 1: performs the chip program. sera sector program active bit. 0: not performs the sector program. 1: performs the sector program. therefore, when sffr=22h, the mcu will perform the sector-erase, sffr=44h, the mcu will perform the chip- erase, and sffr=88h, the mcu will perform the byte-program. for a detailed explanation of mcu flash control, please refer to section 5.1, ?in-application programming? on page 21. core timer counter register (ctcr) location 76543210 reset value 0009h ctd7 ctd6 ctd5 ctd4 ctd3 ctd2 ctd1 ctd0 00h superflash function register (sffr) location 76543210 reset value 000bh pren meren seren - prog mera sera - 00h
advance information remote controller mcu sst65p542r 15 ?2001 silicon storage technology, inc. s71170-03-000 12/01 368 symbol function cwt_en cop watchdog timer enable bit. 0: cop watchdog timer is enabled. 1: cop watchdog timer is disabled. symbol function cwt_clr this bit is for writing only. for detail explanation of cop watchdog timer reset, please refer to section 6.4 0: write zero to this bit will clear cop watchdog timer. 1: write one to this bit has no effect. read this bit will always returns one. symbol function iroln iro latch control bit. reading iroln bit reads the state of the iro latch. writing iroln updates the iro latch with the data being written on the negative edge of the internal processor clock (f osc /2). the iro latch is clear out of reset. writing to chr1 to update iroln will also update the primary carrier high data value. in addition, writing to chr1 to update iroln will update the cmt polarity bit. bit 6 should contain the data of cmtpol polarity bit. cmtpol cmt output polarity bit. this bit controls the polarity of the cmt output (iro). 0: the cmt output is active high. 1: the cmt output is active low. ph[5:0] primary carrier high time data values. when selected, these bits contain the number of input clocks required to generate the carrier high time periods. when operating in timer mode, chr1 and clr1 are always selected. when operating in fsk mode, chr1, clr1 and chr2, clr2 are alternately selected under control of the modulator. the primary carrier high and low time values are undefined on the reset. these bits must be written to non-zero values that before the carrier generator is enabled to avoid spurious results. bit 0 to bit 7 of chr1 can be used for both reading and writing. note: ?u? indicates that the bit is unaffected after reset. cop watchdog timer control register (cwtc) location 76543210 reset value 000dh -------cwt_en 01h cop watchdog timer reset register (cwtr) location 76543210 reset value 3ff0h ------- cwt_clr 01h carrier generator high data register1 (chr1) location 76543210 reset value 0010h iroln cmtpol ph5 ph4 ph3 ph2 ph1 ph0 00uuuuuub
16 advance information remote controller mcu sst65p542r ?2001 silicon storage technology, inc. s71170-03-000 12/01 368 symbol function irolp iro latch control bit. reading irolp bit reads the state of the iro latch. writing irolp updates the iro latch with the data being written on the negative edge of the internal processor clock (f osc /2). writing to clr1 to update irolp will also update the primary carrier low data value. care should be taken that bits 5-0 of the data to be written to chr1 or clr1. pl[5:0] primary carrier low time data values. the function of these bits is the same as ph[5:0]. symbol function sh[5:0] secondary carrier high time data values. when selected, these bits contain the number of input clocks required to generate the carrier high time periods. when operating in time mode, chr2 and clr2 is never selected. when operating in fsk mode, chr2, clr2 and chr1, clr1 are alternately selected under control of the modulator. the secondary carrier high and low time values are undefined on the reset. these bits must be written to nonzero values before the carrier generator is enabled when operating in fsk mode. symbol function sl[5:0] secondary carrier low time data values. the function of these bits is the same as sh[5:0]. carrier generator low data register1 (clr1) location 76543210 reset value 0011h irolp - pl5 pl4 pl3 pl2 pl1 pl0 00uuuuuub carrier generator high data register2 (chr2) location 76543210 reset value 0012h - - sh5 sh4 sh3 sh2 sh1 sh0 00uuuuuub carrier generator low data register2 (clr2) location 76543210 reset value 0013h - - sl5 sl4 sl3 sl2 sl1 sl0 00uuuuuub
advance information remote controller mcu sst65p542r 17 ?2001 silicon storage technology, inc. s71170-03-000 12/01 368 symbol function eoc end of modulation cycle status bit. this bit is read only. eoc is set when a match occurs between the contents of the space period register sreg and the down counter. at the end of cycle, the counter is initialized with the contents of the mark period buffer, mbuff and sreg is loaded with the space period buffer sbuff. this flag is cleared by reading the mcsr followed by an access of mdr2 or mdr3. eoc is cleared by reset. 0: current modulation cycle in progress. 1: end of modulator cycle has occurred. div2 divide by two scaler bit. the divide-by-two prescaler causes the cmt to be clocked at the bus rate, when the two times of bus rate is enabled and the f osc is disabled. since this bit is not double buffered, this bit should not be set during a transmission. 0: divide-by-two prescaler disabled. 1: divide-by-two prescaler enabled. eimsk external interrupt mask bit. this bit is used to mask irq and keyscan interrupts. this bit is cleared by reset. 0: irq and keyscan interrupts enabled. 1: irq and keyscan interrupts disabled. exspc extended space enable bit. for detailed description of extended space operation, please refer to 65p542r programming user?s manual. 0: extended space disabled. 1: extended space enabled base baseband enable bit. this bit disables the carrier generator and forces the carrier output high for generation of baseband protocols. when base is cleared, the carrier generator is enabled and the carrier output toggles at the frequency determined by values stored in the carrier data registers. this bit is cleared by reset. this bit is not double buffered and should not be written during a transmission. 0: baseband disabled. 1: baseband enabled. mode mode select bit. this bit is cleared by reset. this bit is not double buffered and should not be written during a transmission. 0: cmt operates in time mode. 1: cmt operates in fsk mode. eocie interrupt enable bit. interrupt request will be generated when eoc is set and eocie is set. otherwise, interrupt will not be generated 0: interrupt disabled. 1: interrupt enabled. mcgen modulator and carrier generator enable bit. set this bit will initialize the carrier and modulator and will enable all clocks. once enabled, the carrier generator and modulator will function continuously. 0: if this bit is zero, the current modulator cycle will be allowed to expire before all carrier and modulator clocks are disabled and the modulator output is forced low. to prevent spurious operation, the user should initialize all data and control registers before enabling the system. this bit is cleared by reset. all bits except bit 0 can be used for both reading and writing. 1: modulator and carrier generator enabled. modulator control and status register (mcsr) location 76543210 reset value 0014h eoc div2 eimsk exspc base mode eocie mcgen 00h
18 advance information remote controller mcu sst65p542r ?2001 silicon storage technology, inc. s71170-03-000 12/01 368 symbol function mb[11:8] mbuff high 4 bits. sb[11:8] sbuff high 4 bits. these bits can be used for both reading and writing. symbol function mb[7:0] mbuff lower 8 bits. these bits can be used for both reading and writing. symbol function sb[7:0] sbuff lower 8 bits. the bits can be used for reading and writing. symbol function en this bit enable or disable mcu to stop and idle mode. this bit can be used for both reading and writing. 0: stop and idle mode enable 1: stop and idle mode disable. stop stop mode enable bit 0: write 0 to this bit will make the device entering the stop mode if en=0 1: write 1 to this bit has no effect. read returns one. idl idle mode enable bit 0: write 0 to this bit will make the device entering the idle mode if en=0 1: write 1 to this bit has no effect. read returns one. modulator data register 1 (mdr1) location 76543210 reset value 0015h mb11 mb10 mb9 mb8 sb11 sb10 sb9 sb8 uuuuuuuub modulator data register 2 (mdr2) location 76543210 reset value 0016h mb7 mb6 mb5 mb4 mb3 mb2 mb1 mb0 uuuuuuuub modulator data register 3 (mdr3) location 76543210 reset value 0016h sb7 sb6 sb5 sb4 sb3 sb2 sb1 sb0 uuuuuuuub power saving control register (pscr) location 76543210 reset value 0018h en-----stopidl 10000011b
advance information remote controller mcu sst65p542r 19 ?2001 silicon storage technology, inc. s71170-03-000 12/01 368 3.2 sram there are 352 bytes of sram available. the sram addresses start from location 0020h to 017fh. the stack pointer can address 64 bytes of stack beginning at address location 00ffh and ending at 00c0h. 3.3 superflash memory the sst65p542r has 16 kbyte of superflash eeprom memory. the memory is organized as 128 sectors of 128 bytes each. the minimum erasable memory unit is one sector or 128 bytes. the user programmable flash memory occupies the address space from c000h to ff7fh. the user vector area consists of 128 bytes starting from address location ff80h to ffffh. address ff80h is for flash memory read protection. there are five predeter- mined user vectors from fff6h through ffffh dedicated to the reset and interrupts. every vector consists of two bytes to be loaded into program counter for jumping to an interrupt service routine (isr). see table 3-5 for detailed descriptions of these vectors. table 3-5: i nterrupt /r eset s ector address location user vectors ff80h flash memory read protection ff81h-fff5h unused fff6h core timer vector - (high byte) fff7h core timer vector - (low byte) fff8h cmt vector (high byte) fff9h cmt vector (low byte) fffah irq/port b vector (high byte) fffbh irq/port b vector (low byte) fffch swi vector (high byte) fffdh swi vector (low byte) fffeh reset vector (high byte) ffffh reset vector (low byte) t3-5.5 368
20 advance information remote controller mcu sst65p542r ?2001 silicon storage technology, inc. s71170-03-000 12/01 368 4.0 parallel input/output ports 4.1 port a port a consists of eight individual pins driven by one data register and one direction register to control the usage of these pins as either inputs or outputs. all port a pins are set to input mode during any reset. software must set the right direction register first before performing any read or write operation. any read operation to the port that was set as output will read back the data from an internal latch register instead of the i/o pins. for details, please refer to section 3.1 port a data register and port a data direction register. 4.2 port b port b pins are similar to port a pins except that each of the port b pins has a programmable interrupt generation option which can be enabled for any port b pins. port b pins have optional programmable pull-ups. there is a choice between pull-up strengths which could be selected by pu0 or pu1. for details, please refer to section 3.1, port b interrupt control register and port b pull-up control register. figure 4-1: p ort b i nterrupt and p ull -u p o ptions 4.3 port c port c is a 4-bit bi-directional port (pc3-pc0). every port c pin has high current driving capability. reset clears the port c data register and the data direction register, thereby returning the ports to inputs. for details, please refer to section 3.1 port c data register and port c data direction register. weak1 interrupt logic 368 ill f03.3 . . . inprb7 ddrb7 from all other port b pins weak0 pu0 pu1 pb7 v dd
advance information remote controller mcu sst65p542r 21 ?2001 silicon storage technology, inc. s71170-03-000 12/01 368 5.0 flash memory programming 5.1 in-application programming sst65p542r allows ?in-application programming? (iap) to update the user code in the internal 16 kbyte super- flash memory. all write/erase operations require setting the enable bit in the superflash function register (sffr) located at 000bh. the following sections describe the operations that the mcu performs to alter the contents of superflash memory. for detailed explanation of the super- flash function register, please refer to section 3.1. 5.1.1 chip-erase the chip-erase operation requires meren and mera bits to be set to logical ?1?. after setting these bits, writing any data to any address location of the flash memory will trigger the chip-erase operation. the mcu is idle while sst65p542r is busy doing erases on all memory loca- tions. 5.1.2 sector-erase the sector-erase operation requires seren and sera bits to be set to logical ?1?. after setting these bits, writing any data to the address within the sector to be erased will erase the data in the sector. the mcu is idle while sst65p542r is busy doing erase on the sector. 5.1.3 byte-program the byte-program operation requires pren and prog bits to be set to logical ?1?. after setting these bits, and then writing the data to the target address to be programmed. the mcu is idle while sst65p542r is busy doing pro- gramming on the byte. refer to the following summary for all different functions. . 5.2 external host programming mode the external host programming mode is to provide pro- grammer access to the 16kb embedded flash memory of the sst65p542r. to enter the external host programming mode, users must follow the setup sequences on the pins (see figure 11-1): 1. ry/by# (pin 12) and porout# (pin 13) are out- put pins. do not drive. 2. drive rst# (pin 24) low. 3. drive lprst# (pin 21) low. 4. drive lprst# (pin 21) high after t rst . 5. drive prog_rst (pin 9) low. 6. drive 9 clocks on tclkin. on each clock's rising edge provide one bit of data on tdin (pin 19) as shown in figure 11-1. the data bits are ?11010011?. 7. wait for ry/by# (pin 12) and porout# to go high. 8. drive at least 24 clocks on tclkin. 9. if read-protect byte is set, then ry/by# will go low. otherwise, ry/by# will stay high. if ry/by# is low, wait for ry/by# (pin 12) to go high. now the sst65p542r is in external host programming mode and is ready for embedded flash read or write operations. now the sst65p542r is in the external host programming mode and is ready for embedded flash by the external host read or write. as soon as the rst# is released to ?1?, chip exits external host programming mode and then enters user mode. 5.2.1 external host mode read operation as shown in figure 11-2, the read operation needs two address setup cycles and one data setup cycle. the low to high transition on sclk latches the high order address a[13:8] from the pin ad[5:0] while mode[1:0] inputs are set to 0h; the low to high transition on sclk latches the low order address a[7:0] from the pin ad[7:0] while the mode[1:0] inputs are set to 3h and setting the signal oe# to low; the low to high transition on sclk latches the data d[7:0] on the pin ad[7:0] while the mode[1:0] is set to 1h for reading. after reading the data, the external host should set the signal oe# to high. table 5-1: sffr c ommands function command writes to sffr comment chip-erase 44h erase the whole flash memory sector-erase 22h erase the sector addressed by cxxxh byte-program 88h program one data byte to address cxxxh. write data to cxxxh before byte-program can be performed, a chip-erase or sector-erase must be issued to erase the target programming locations. t5-1.1 368
22 advance information remote controller mcu sst65p542r ?2001 silicon storage technology, inc. s71170-03-000 12/01 368 5.2.2 external host mode write operation as shown in figure 11-3, the write operation needs two address setup cycles and one data setup cycle. the low to high transition on sclk latches the high order address a[13:8] from the pin ad[5:0] while the mode[1:0] inputs are set to 0h; the low to high transition on sclk latches the low order address a[7:0] from the pin ad[7:0] while mode[1:0] inputs are set to 2h; the low to high transition on sclk latches the data d[0:7] from the pin ad[7:0] while the mode[1:0] is set to 1h for writing. however, the actual write operation to embedded flash memory occurs on the rising edge of we#. 5.2.3 external host mode byte-program operation this device is programmed on a byte by byte basis. the byte-program operation consists of three steps. the first step is the three-byte load sequence for software data pro- tection. the second step is to load the byte address and the byte data. the third step is the internal program opera- tion which is initiated after the rising edge of the fourth we#. the end of the byte-program operation can be determined by using the ry/by#. any commands written during the byte-program operation will be ignored. see table 5-4 for the software command sequence, figure 11-5 for the flash byte-program timing diagram, and figure 11-9 for the byte-program command sequence flowchart. 5.2.4 external host mode chip-erase operation. the device provides a chip-erase operation, which allows the user to erase the entire memory array to the ?1?s state. this is useful when the device must be quickly erased entirely. the chip-erase operation is initiated by executing a six-byte software data protection command sequence, the last byte sequence is the address 1555h with the chip- erase command 10h. the chip-erase operation begins with of the sixth write enable?s (we#) rising edge. the end of the chip-erase can be determined by using the signal ry/by#. any commands written during the chip-erase operation will be ignored. see table 5-4 for the software command sequence, figure 11-4 for the flash chip-erase timing diagram, and figure 11-11 for the chip-erase com- mand sequence flowchart. 5.2.5 external host mode sector-erase operation the sector-erase operation allows the system to erase the device on a sector-by-sector basis. the sector architecture is based on uniform sector size of 128 bytes. the sector- erase operation is initiated by executing a six-byte com- mand sequence for software data protection, the last byte sequence is the sector address sa with the sector-erase command 30h. the address lines a[13:7] will be used to determine the sector address. the internal erase operation begins after the sixth write enable?s (we#) rising edge. the end-of-erase can be determined by using the signal ry/ by#. any commands written during the sector-erase oper- ation will be ignored. see table 5-4 for the software com- mand sequence, figure 11-5 for the flash sector-erase timing diagram, and figure 11-11 for the sector-erase command sequence flowchart. table 5-2: e xternal h ost p rogramming m ode p in d escriptions pins symbol type 1 1. i = input; o = output name and functions 8-1 ad[7:0] i/o 1 embedded flash memory address and data bus multiplex on ad[7:0] by selecting mode[1:0] 10,20 mode[1:0] i address and data bus selection bits in the external host programming mode 11 slck i clock for latch address and data after entering the external host programming mode 9 prog_rst i reset signal for the external host programming mode 13 porout# o embedded flash memory power-on reset output 12 ry/by# o embedded flash ready/busy output. high is ready 17 we# i write enable: embedded flash memory data write enable, low active 18 oe# i output enable: embedded flash memory data out enable, low active 21 lprst# i signal for entering the external host programming mode 19 tdin i data input for entering the external host programming mode 23 tclkin i this clock will latch tdin for entering the external host programming mode 22 v ss pwr ground: circuit ground (0v reference) 26 v dd pwr power supply: supply voltage (3.2v) t5-2.3 368
advance information remote controller mcu sst65p542r 23 ?2001 silicon storage technology, inc. s71170-03-000 12/01 368 5.2.6 operation status detection - program timer method during the program or erase operation, the programmer can use the timer to decide the completion of the operation. when a program or erase operation is started, system set- up a timer for t bp (for byte-program), t sce (for chip- erase), and t se (for sector-erase) time period. after this timer time-out, the operation is completed. see figure 11- 10 for program timer flowchart. 5.2.7 operation status detection - ry/by# method during the internal program or erase operation, the signal ry/by# indicates the status of the operation. when the internal program or erase operation is in progress, the sig- nal ry/by# will be driven low. when the internal program or erase operation is completed, the signal ry/by# will be driven high. the device is then ready for the next operation. see figure 11-10 for the program timer flowchart. 5.2.8 exiting the external host programming mode to exit the external host programming mode, the external host must set the rst# pin to high, and the prog_rst is reset to high. the device will exit the host programming and enter the user mode. the mcu starts execution codes out of the user memory space from the reset vector. 5.2.9 flash read protection to protect the program code from piracy the flash memory location 3f80h (user memory address ff80h, flash mem- ory is mapped to c000h through ffffh, see figure 3-1) is evaluated by the internal hardware to determine the read protect mode state. during this evaluation period, only the ry/by# pin is valid and all other pins are blocked. if this byte is a3h (read protect is active), a chip-erase will be performed by internal hardware before the external host programming mode is activated. while the chip-erase could take t sce (see table 11-5) as maximum time, users may use ry/by# pin to determine the completion of the chip-erase. if this byte is not a3h (not read protected), all of the flash memory are visible by using the external host programming. during the internal program or erase opera- tion, the signal ry/ by# indicates the status of the opera- tion. when the internal program or erase operation is in progress, the ry/by# will be driven low. when the internal program or erase operation is completed, the ry/by# will be driven high. the device is then ready for the next opera- tion. see figure 11-10 for the program timer flowchart. note: after writing a3h to the flash read protection register, the device needs to continue power-on prior to finishing the programming function. the programming function may include the program-verify function. table 5-3: e xternal h ost p rogramming m ode p in a ssignment mode0=0 mode1=0 mode0=0 mode1=1 mode0=1 mode1=0 mode0=1 mode1=1 ad[0] input a8 input a0 input d0 output d0 ad[1] input a9 input a1 input d1 output d1 ad[2] input a10 input a2 input d2 output d2 ad[3] input a11 input a3 input d3 output d3 ad[4] input a12 input a4 input d4 output d4 ad[5] input a13 input a5 input d5 output d5 ad[6] input a6 input d6 output d6 ad[7] input a7 input d7 output d7 t5-3.1 368 table 5-4: s oftware c ommand s equence command sequence 1st bus write cycle 2nd bus write cycle 3rd bus write cycle 4th bus write cycle 5th bus write cycle 6th bus write cycle addr 1 1. address format a 13 -a 0 (hex) data addr 1 data addr 1 data addr 1 data addr 1 data addr 1 data sector-erase 1555h aah 2aaah 55h 1555h 80h 1555h aah 2aaah 55h sa x 2 2. sa x for sector-erase; uses a 13 -a 7 address lines 30h chip-erase 1555h aah 2aaah 55h 1555h 80h 1555h aah 2aaah 55h 1555h 10h byte-program 1555h aah 2aaah 55h 1555h a0h wa 3 3. wa = program byte address data t5-4.3 368
24 advance information remote controller mcu sst65p542r ?2001 silicon storage technology, inc. s71170-03-000 12/01 368 6.0 reset the 65p542r can be reset from five sources: two external inputs and three internal restart conditions. figure 6-1: r eset b lock d iagram 6.1 external reset a low-level input on the rst# pin causes the program counter to be set to the contents of location fffeh and ffffh (reset vector). the mcu is initialized to a known state. stack pointer will be reset to ffh. hardware reset is the highest priority input to the chip. an internal schmitt trigger is implemented on the rst# input to enhance the noise immunity. 6.2 external low power reset the lprst# is one of the two external sources of a reset. the signal lprst# allows the mcu to go into low power reset mode. all clocks and oscillator to the processor are halted when the lprst# is held low. after the lprst# is de-asserted (driven high), a delay of 4064 bus clock cycles is automatically enabled to wait for stable crystal oscillation. this pin also implements an internal schmitt trigger to enhance the noise immunity. 6.3 internal power-on and brown-out reset the internal reset signal will reset the cpu and all peripheral components. please refer to figure 6-1. when the device is powered up, the internal power-up voltage is 2.0-2.2v. in addition, the internal brown-out voltage is set to 1.9-2.1v. if the voltage is below the threshold values, the device will reset in order to protect against the inad- vertent write to the flash memory. 6.4 cop watchdog timer reset sst65p542r has a cop (computer operating properly) watchdog timer for monitoring the proper operations of mcu. in normal operation, clearing the cop watchdog timer is executed by software within a preset period of time to avoid reaching time-out condition. to clear the cop watchdog timer, software write ?0? to location 3ff0h. the cop watchdog reset is asserted and resets the mcu when the time-out condition occurs. the cop watchdog timer is disabled during any external reset. to enable cwt, write logical ?0? to cwt control register (000dh). refer to the sst65p542r programming user?s manual for more information. 6.5 illegal address reset an illegal address reset is generated when the mcu attempts to fetch an instruction from i/o address space (0000h to 001fh). those addresses are reserved for i/o registers only. 368 ill f16.2 osc address rst# lprst# illegal address reset 4064 bus clock cycle delay cop watchdog reset reset control internal reset address data
advance information remote controller mcu sst65p542r 25 ?2001 silicon storage technology, inc. s71170-03-000 12/01 368 7.0 interrupts sst65p542r accepts five sources of interrupts with high- est to lowest priority: software interrupt, external interrupts (irq# pin / port b), cmt interrupt, and core timer inter- rupt. whenever multiple interrupt requests are active at the same time, the higher priority one will be serviced first. all interrupts are maskable except software interrupt which is generated by executing swi instruction. to mask inter- rupts, set the interrupt mask bit of process status word (psw). before serving the interrupt, the mcu registers are pushed onto the stack in the sequence of pcl, pch, idx, acc, psw. the interrupt service routine should clear the source of interrupt before exiting. by executing rti instruc- tion, the stored mcu registers are popped from the stack and the program resumes from the interrupted location. 7.1 software interrupt the swi instruction causes mcu to load the contents of memory locations fffch and fffdh into program counter regardless of the interrupt mask bit in psw register. 7.2 external interrupts upon completion of the current instruction, the mcu responds to the interrupt request that is latched internally. irq# must be asserted (low) for at least one t ilih (125 ns). following the completion of the current instruction, the interrupt latch is tested. if both interrupt mask bit (i bit) in the psw is clear and the interrupt request is pending, the inter- rupt service routine is entered. an external resistor to v dd is required by the irq# input for wired-and operation. the external interrupts, irq# pin and port b interrupts are edge-sensitive and asserted on the falling edge of the pins. the port b interrupt control register enables or disables interrupts on each individual pin of port b. the external interrupt mask bit (eimsk) of modulator control and sta- tus register can be used to mask all external interrupts so that lower priority interrupts such as timer interrupts can be served. the state of any external interrupt received during the masked period is preserved. when the eimsk bit is clear, the pending interrupts activate the mcu interrupt pro- cessing again. the external interrupt causes mcu to load the contents of memory locations fffah and fffbh into program counter. 7.3 cmt interrupt a cmt interrupt is generated when the end of cycle flag (eoc) and the end of cycle interrupt enable (eocie) bits are set in the modulator control and status register (mcsr). this interrupt will vector to the interrupt service routine located at the address specified by the contents of memory locations fff8h and fff9h. 7.4 core timer interrupt the core timer is a 14-stage multifunctional ripple timer. user can select overflow or real-time interrupt by the setting of the core timer control status register. please see the timer section for more details. the timer interrupt causes mcu to load the contents of memory locations fff6h and fff7h into program counter.
26 advance information remote controller mcu sst65p542r ?2001 silicon storage technology, inc. s71170-03-000 12/01 368 8.0 operation modes the device can operate in two different modes. the opera- tion mode includes the user mode and the learning mode. the pin definitions vary between different operation modes as described in table 8-1. 8.1 user mode in the user mode, the embedded mcu fetches program codes from the user memory space. please refer to the sst65p542r programming user?s manual for instruction sets and the internal mcu programming information. 8.2 learning mode to enter the learning mode, input the ir signal to the irq# pin, then use the bil and bih instruction set to record the input signal width. for detail information on learning mode, please refer to the application note ?remote controller learning algorithm using sst65p542r.? table 8-1: p in a ssignment f or d ifferent o peration m odes pin # normal interface modes external host programming mode 1 1. see table 5-2 for pin description. user mode learning mode 1 pb[0] pb[0] ad[0] 2 pb[1] pb[1] ad[1] 3 pb[2] pb[2] ad[2] 4 pb[3] pb[3] ad[3] 5 pb[4] pb[4] ad[4] 6 pb[5] pb[5] ad[5] 7 pb[6] pb[6] ad[6] 8 pb[7] pb[7] ad[7] 9 pa[0] pa[0] prog_rst 10 pa[1] pa[1] mode[1] 11 pa[2] pa[2] sclk 12 pa[3] pa[3] ry/by# 13 pa[4] pa[4] porout# 14 pa[5] pa[5] v il 15 pa[6] pa[6] v il 16 pa[7] pa[7] v ih 17 pc[0] pc[0] we# 18 pc[1] pc[1] oe# 19 pc[2] pc[2] tdin 20 pc[3] pc[3] mode[0] 21 lprst# lprst# lprst# 22 v ss v ss v ss 23 iro iro tclkin 24 rst# rst# v il 25 irq# irin v ih 26 v dd v dd v dd 27 osc2 osc2 do not use 2 2. osc2 is an output, not used during external host program mode. 28 osc1 osc1 v il t8-1.8 368
advance information remote controller mcu sst65p542r 27 ?2001 silicon storage technology, inc. s71170-03-000 12/01 368 9.0 peripherals and others 9.1 core timer core timer provides the following features: 1. real time interrupt (rti) 2. timer overflow 3. cop watchdog timer 4. power-on reset (por) please refer to sst65p542r programming user?s manual for programming information. 9.2 carrier modulator transmitter (cmt) sst65p542r integrates a carrier modulator transmitter for supporting various encoding methods. the purpose of this module is to reduce the loading of the mcu. three major functions are performed by this block: carrier generation, modulation, and transmission. please refer to sst65p542r programming user?s manual for programming information. 9.3 clock input options control connections for the 2-lead on-chip oscillator are the osc1 and osc2 pins. osc1 is input and osc2 is output. a crystal resonator, ceramic resonator, or external clock signal can drive the oscillator. 9.4 crystal/ceramic resonator a crystal/ceramic oscillator circuit is shown in figure 9-1. a ceramic resonator instead of a crystal may be used to reduce costs. it is recommended that the resonator and capacitors be mounted as close to the pins as possible to minimize output distortion. crystal manufacturer, supply voltage, and other factors may cause circuit performance to differ from one appli- cation to another. c1 and c2 should be adjusted appropriately for each design. figure 9-1: u sing the c rystal figure 9-2: e xternal c lock d rive 9.5 external clock drive if external clock source is provided, osc1 is the clock input and osc2 is don?t connect. leave osc2 open. 368 ill f05a.6 osc1 4.0 mhz 5 m ? osc2 v ss 30 pf 30 pf 368 ill f05b.3 osc2 osc1 v ss external clock signal don't connect
28 advance information remote controller mcu sst65p542r ?2001 silicon storage technology, inc. s71170-03-000 12/01 368 10.0 power saving modes sst65p542r provides two power saving modes: stop mode and idle mode. these two modes can be entered through the setting of the power saving control register. refer to section 3.1 for power saving control register. 10.1 stop mode writing a logic ?0? to the stop bit of the power saving con- trol register enters the stop mode. to achieve the lowest possible power consumption, the implementation uses stop bit to gate off the internal clock. see figure 10-1 for illustration of clock arrangement in the stop mode. since there is no clock input, the internal states are maintained and not changed including i/o registers and ram memory except that the core timer counter bits are cleared. the external irq interrupt can brought the device out of the stop mode, but all other interrupts are not served until the device is recovered from stop mode. there are three conditions that will recover the device from the stop mode: external irq#/port b interrupt (eimsk=0), rst# or external reset lprst#. the stop bit will be set to 1 when the device has been brought out of stop mode. the inter- rupt mask bit (i bit) will not be affected. 10.2 idle mode writing a logic ?0? to the idle bit of the power saving con- trol register enters the idle mode. in the idle mode, the timer is still running. any internal or external interrupt will recover the device from idle mode. if both stop and idle bits are ?0?, then stop mode takes effect. the idle bit will be set to 1 when the device has been brought out of the idle mode. the interrupt mask bit (i bit) will not be affected. figure 10-1: s top m ode and i dle m ode cpu idle clock generator 2 clk stop peripherals 368 ill f04.2
advance information remote controller mcu sst65p542r 29 ?2001 silicon storage technology, inc. s71170-03-000 12/01 368 11.0 electrical specification 11.1 absolute maximum stress ratings 11.2 reliability characteristics 11.3 dc specifications absolute maximum stress ratings (applied conditions greater than those listed under ?absolute maximum stress ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. exposure to absolute maximum stress rating conditions may affect device reliability.) ambient temperature under bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55c to +125 c storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65 c to + 150 c dc voltage on any pin to ground potential. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0. 5v to v dd +0.5v transient voltage (<20 ns) on any pin to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0v to v dd +1.0v package power dissipation capability (t a = 25 c). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0w surface mount lead soldering temperature (3 seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 c output short circuit current 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 m a 1. outputs shorted for no more than one second. no more than one output shorted at a time. (based on package heat transfer limitations, not devices power consumption.) table 11-1: r eliability c haracteristics symbol parameter minimum specification units test method n end endurance 10,000 cycles jedec standard a117 t dr 1 1. the parameter is measured only for initial qualification and after a design or process change that could affect this paramete r. data retention 100 years jedec standard a103 i lt h 1 latch up 100+i dd ma jedec standard 78 t11-1.3 368 table 11-2: r ecommended dc o perating c onditions (t a = 0c to +70c) symbol parameter min max unit v dd supply voltage 2.2 3.2 v t a temperature 0 +70 c f osc osc. frequency 0 8 mhz t11-2.0 368
30 advance information remote controller mcu sst65p542r ?2001 silicon storage technology, inc. s71170-03-000 12/01 368 11.4 dc electrical characteristics table 11-3: dc e lectrical c haracteristics (t a = 0c to +70c, v dd = 2.2-3.2v, v ss = 0v) symbol parameter min max typ unit i dd 1 1. test conditions for i dd are 8 mhz and 20 pf loading. supply current run without flash erase/program operation - 8 2.5 ma run with flash erase/program operation - 20 10 ma idle 2 2. idle current i dd is 0.4 ma typical, 0.6 ma maximum at 4 mhz, 2.2v, and 20 pf loading. 2.75 0.8 ma stop 25 6 4 a 0to +70 15 9 a i oz i/o ports hi-z leakage current port a, port b, port c -2 2 - a i in input current irql, resetl, lprstl, osc1 -1 1 - a port b with strong pull-ups enable (v in = 0.2xv dd ) -34 -74 -50 port b with strong pull-ups enabled (v in = 0.8xv dd ) -15 -36 -25 port b with weak pull-ups enable (v in = 0.2xv dd ) -17 -37 -25 port b with weak pull-ups enabled (v in = 0.8xv dd ) -7.5 -18 -12.5 output voltage v ol (i load = 1 ma) osc2 - 0.4 - a v oh (i load = -500 a) osc2 v dd -0.4 - - v oh output high voltage (i load = -1.2 ma) port a, port b v dd -0.4 v dd -0.3 v (i load = -6 ma) iro v dd -0.8 v dd -0.3 (i load = -4 ma) port c v dd -0.5 v dd -0.3 v ol output low voltage (i load = 1.8 ma) port a, port b 0.4 0.2 v (i load = 12 ma) iro 0.8 0.3 (i load = 8 ma) port c 0.5 0.3 v ih input high voltage port a, port b, port c, osc1 0.8 v dd v dd -v irql, resetl, lprstl 0.8 v dd v dd - v il input low voltage port a, port b, port c, osc1 v ss 0.2 v dd -v irql, resetl, lprstl v ss 0.2 v dd - t11-3.3 368
advance information remote controller mcu sst65p542r 31 ?2001 silicon storage technology, inc. s71170-03-000 12/01 368 11.5 ac electrical characteristics table 11-4: c ontrol t iming (t a = 0c to +70c, v dd = 2.2 to 3.2v, v ss = 0v) symbol characteristic min max unit frequency of operation f osc crystal 8 mhz f ext external clock 8 mhz f op internal operating frequency 4 mhz t cyc cycle time 125 ns t oxov 1 1. guaranteed by design. crystal oscillator startup time 100 ms t ilch 1 stop recovery startup time 100 ms t rl 1 rst# pulse width 1.5 t cyc t ilih 1 interrupt pulse width low (edge-triggered) 125 ns t oh ,t ol 1 osc1 pulse width 90 ns t11-4.2 368 table 11-5: e xternal h ost p rogramming -m ode t iming p arameters symbol parameter min max units t as 1 1. guaranteed by design. address/data setup time 30 ns t cp 1 sclk cycle time 130 ns t ah 1 address/data hold time 45 ns t cph 1 sclk pulse width high 65 ns t se sector-erase time 2 2. applies to iap as well 25 ms t sce chip-erase time 2 100 ms t bp byte-program time 2 80 s t dh 1 tdin hold time 45 ns t ds 1 tdin setup time 30 ns t dp 1 tclkin pulse width 65 ns t dph 1 tclkin pulse width high 65 ns t rst 1 reset time 720 ns t oe 1 output enable time 50 ns t wes 1 address latch setup time 65 ns t weh 1 data latch setup time 30 ns t aa 1 read access time 65 ns t11-5.6 368
32 advance information remote controller mcu sst65p542r ?2001 silicon storage technology, inc. s71170-03-000 12/01 368 figure 11-1: e xternal h ost p rogramming m ode - s etup c ycle t iming d iagram figure 11-2: e xternal h ost p rogramming m ode - r ead c ycle t iming d iagram 368 ill f06.13 t clkin (pin 23) reset# (pin 24) osc1 (pin 8) lprst# (pin 21) prog_rst (pin 9) tdin (pin 19) sclk (pin 11) we#/oe# (pins 17, 18) ry/by# (pin 12) porout# (pin 13) t dp t dph t dh t rst t ds 0001 1 1 1 1 24 clocks t sce 1 1. low if read-protect byte is set. x x x x x x x x x t as t ah t oe 0 a[13:8] a[7:0] data 2 3 368 ill f07b.9 sclk (pin 11) ad[7:0] (pin 8-1) mode[1:0] (pin 10, 20) oe# (pin 18) we# (pin 17) t cph t aa t cp x x x x x x x x x x
advance information remote controller mcu sst65p542r 33 ?2001 silicon storage technology, inc. s71170-03-000 12/01 368 figure 11-3: e xternal h ost p rogramming m ode - w rite c ycle t iming d iagram figure 11-4: e xternal h ost p rogramming m ode - c hip -e rase t iming d iagram t cph t ah 0 a[13:8] a[7:0] data/cmd 21 368 ill f07a.10 sclk (pin 11) ad[7:0] (pin 8-1) mode[1:0] (pin 10, 20) oe# (pin 18) we# (pin 17) t wes t as t weh t cp t ds t dh x x x x x x x x x x x x x x x x x x x x x x 368 ill f08.9 ad[7:0] mode[1:0] we# sclk 15 55 55 15 55 15 55 55 15 55 10 80 aa aa aa 2a aa 2a six-byte write command for chip-erase 02 102 02 1021 1 12 1 02 0 t sce ry/by#
34 advance information remote controller mcu sst65p542r ?2001 silicon storage technology, inc. s71170-03-000 12/01 368 figure 11-5: e xternal h ost p rogramming m ode s ector -e rase t iming d iagram figure 11-6: e xternal h ost p rogramming m ode b yte -p rogram t iming d iagram note: sa h and sa l = sector address, a 13 -a 7 are used 368 ill f09.9 ad[7:0] mode[1:0] sclk 15 55 55 15 55 15 55 55 sa h sa l 30 80 aa aa aa 2a aa 2a six-byte write command for sector-erase 02 102 02 1021 1 12 1 02 0 t se we# ry/by# note: ba h ba l = byte address, a 13 -a 0 are used 368 ill f10.9 ad[7:0] mode[1:0] sclk 15 55 55 15 55 ba h ba l data a0 aa aa 2a four-byte write command for byte-program 02 102 021 1 12 0 t bp we# ry/by#
advance information remote controller mcu sst65p542r 35 ?2001 silicon storage technology, inc. s71170-03-000 12/01 368 figure 11-7: ac i nput /o utput r eference w aveform figure 11-8: a t est l oad e xample 368 ill f14.0 reference points output input v it v iht v ilt v ot ac test inputs are driven at v iht (0.9 v dd ) for a logic ?1? and v ilt (0.1 v dd ) for a logic ?0?. measurement reference points for inputs and outputs are at v it (0.5 v dd ) and v ot (0.5 v dd ) input rise and fall times (10% ? 90%) are <5 ns. note: v ht - v high te s t v lt - v low te s t v iht - v input high test v ilt - v input low test 368 ill f15.0 to tester to dut c l
36 advance information remote controller mcu sst65p542r ?2001 silicon storage technology, inc. s71170-03-000 12/01 368 figure 11-9: b yte -p rogram c ommand s equence for e xternal h ost p rogramming m ode 368 ill f11.6 start write data: aah address: 1555h write data: 55h address: 2aaah write data: a0h address: 1555h write address data wait for end of program (t bp , ry/by#) program completed
advance information remote controller mcu sst65p542r 37 ?2001 silicon storage technology, inc. s71170-03-000 12/01 368 figure 11-10: w ait o ptions for e xternal h ost p rogramming m ode 368 ill f12.3 wait t bp , t sce, or t se program/erase initiated program timer ye s no program/erase completed ry/by# polling program/erase completed ry/by# = high ry/by# program/erase initiated
38 advance information remote controller mcu sst65p542r ?2001 silicon storage technology, inc. s71170-03-000 12/01 368 figure 11-11: c hip -/s ector -e rase c ommand s equence for e xternal h ost p rogramming m ode 368 ill f13.7 load data: aah address: 1555h chip-erase command sequence load data: 55h address: 2aaah load data: 80h address: 1555h load data: 55h address: 2aaah load data: 10h address: 1555h load data: aah address: 1555h chip erased to ffffh load data: aah address: 1555h sector-erase command sequence load data: 55h address: 2aaah load data: 80h address: 1555h load data: 55h address: 2aaah load data: 30h address: sa x load data: aah address: 1555h wait for end-of-erase (t se, ry/by#) wait for end-of-erase (t sce, ry/by#) sector erased to ffffh
advance information remote controller mcu sst65p542r 39 ?2001 silicon storage technology, inc. s71170-03-000 12/01 368 12.0 product ordering information 12.1 valid combinations SST65P542R-8-C-SG sst65 p 5 4 2 r-8 - c - sg sstxx x x x x x x x xx package modifier g = 28 leads package type s = soic operation temperature c = commercial: 0c to +70c operating frequency 8 = 8.0 mhz function r = remote controller on-chip sram size 2 = 352 bytes flash memory size 4 = 16 kbyte core sub-block 5 = enhanced 6502 core voltage 2.2- 3.2v device family
40 advance information remote controller mcu sst65p542r ?2001 silicon storage technology, inc. s71170-03-000 12/01 368 13.0 packaging diagrams 28- lead s mall o utline ic (soic) sst p ackage c ode : sg 28.soicsg-ill.5 note: 1. complies with jedec publication 95 ms-013 ae dimensions, although some dimensions may be more stringent. 2. all linear dimensions are in millimeters (min/max). 3. coplanarity: 0.1 (.05) mm. 4. maximum allowable mold flash is 0.15mm at the package ends, and 0.25mm between leads. .33 .51 17.70 18.10 1.27 bsc .10 .30 2.36 2.64 .23 .30 0.4 1.27 10.01 10.64 7.40 7.60 pin #1 identifier silicon storage technology, inc. 1171 sonora court sunnyvale, ca 94086 telephone 408-735-9110 fax 408-735-9036 www.superflash.com or www.ssti.com

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